Er, decoupling capacitance (what you describe) doesn't affect power consumption -- at least not anywhere near as much as parasitic capacitance does. Decoupling capacitance smooths out spikes in the supply, but it doesn't increase power consumption (except for leakage).
I agree with you on power, but disagree with you on what it means "process invariant". The way I understand you, you use "process invariant" as "process feature-size invariant", but you disregard the number and the composition of layers.
Bitfury used some cheap digital-only process and laid out the bypass capacitors
beside the flip-flops. Hypothetically he could have used some more expensive mixed-signal process which provides for much thicker metal layers and high-k dielectric between the metal layers (not for the gates). Then he could've laid the bypass capacitors
on top of the flip-flops.
All in all, I think the good definition of "process invariant" metrics is still an open research question. E.g. how we are going to account for the future Intel technologies where they have on-chip buck voltage regulators including planarized magnetics?