You are getting closer to my point. If this is a complete design (and not something more akin to eASIC where you just design one layer), you would typically get on a shuttle (which would mean you would be saying "shuttle run is schedule and we should get sample chips to test and optimize our design in xx days). Then you would spend the $800,000 to tape out a 28nm mask......
who knows? That is what I am saying. we do not know. seems credible but who are the "competitors" that are scared if they know their progress? If I am producing ASICs it does not matter when these guys ship. It just changes the difficulty. It does not help my chips come quicker....
If an MPW batch had been made, then we would have seen a working prototype well before the production wafer run was ordered, that clearly hasn't happened unless they choose to keep it a tight lipped secret, so one would assume it wont and the first sample will be from the production wafers.
Hopefully they're not using ST Micro as their foundary. ST has a bunch of open MPW space (not utilized by contract customers) on August 7th... on their SOI process. Hopefully KNC knows enough to avoid SOI for chips of this nature.