Update:
an video of our FPGA prototype : http://www.btcgarden.com/videos.jsp
We had finished this in May although the video was just made 2 hours ago by our engineers at Xi`An
BTW : YOUTUBE is blocked in mainland china for a long long time,so all chinese shareholders please wait for a youku version later at btcman ,sry
Here s a pic of it
an video of our FPGA prototype : http://www.btcgarden.com/videos.jsp
We had finished this in May although the video was just made 2 hours ago by our engineers at Xi`An
BTW : YOUTUBE is blocked in mainland china for a long long time,so all chinese shareholders please wait for a youku version later at btcman ,sry
Here s a pic of it
Thanks for the video and the update. But why is it hashing at ~500MH/s now? The pic posted by dxxw makes much more sense to me, as that one is showing ~363MH/s, which is more in-line with your chip specs?
Could you also give some more details on the 130nm process you chose to build the chips and final specs? This is very important. You are estimating 1.5W/chip (3.75W/GH) but your chip uses 1.25V@400MH/s (vs 1.2V of an 110nm Avalon for example, and power usage increases by the square of voltage and linearly with frequency, P=C*V^2*f) and I find it intriguing why you need 64 pads if not for extra power?
b) ASIC brief introduction
SMIC 0.13um;
Core Voltage: 1.2V;
I/O: Voltage: 3.3V;
Core Frequencey: 400MH/s;( @vdd 1.25V);
Number of Pads; 64;
Package lqfp64;
SMIC 0.13um;
Core Voltage: 1.2V;
I/O: Voltage: 3.3V;
Core Frequencey: 400MH/s;( @vdd 1.25V);
Number of Pads; 64;
Package lqfp64;
Quote
Avalon chip specs
Technology Summary:
TSMC 0.11- micron G process
5 Metal
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 256+ MHz
Number of Pads: 48
8 Data
40+1 Power
Package Type: QFN48 -0.5 Pitch
Packaged Chip Size: 7 mm x 7 mm
Chip Interface
Data Pins (8 in total):
Clock i
Serial Data In [2] i
Serial Data Out [2] o
Serial Data Bypass [2] o
Reserved [1] -
Chip power efficienty: 6.6W/GHs @ 1.15 V
Technology Summary:
TSMC 0.11- micron G process
5 Metal
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 256+ MHz
Number of Pads: 48
8 Data
40+1 Power
Package Type: QFN48 -0.5 Pitch
Packaged Chip Size: 7 mm x 7 mm
Chip Interface
Data Pins (8 in total):
Clock i
Serial Data In [2] i
Serial Data Out [2] o
Serial Data Bypass [2] o
Reserved [1] -
Chip power efficienty: 6.6W/GHs @ 1.15 V