So the main argument of Mr. Simon Barber why the Hashfast 400 GH/s ASICs are feasible is, that he was assuming that KnC does a 100 GH/s chip based on a structured ASIC (FPGA-hardcopy)? Because he thought that KnC must go with eASIC and eASIC only offers structured ASICs?

I hope Hashfast did not did their target specification based on that wrong assumption and a little silicon valley hubris in the way:
"KnC can realize 100 GH/s based on a hardcopy. So we can do easily 400 GH/s based on a real standard cell ASIC!"

Hashfast also will use multiple instances of pipelined hash core as base. They are not reinventing the wheel. It's still 28nm, a single hash core can't be much smaller as 0.5 mm2 (for sure not based on this poor (hopefully initial) floorplan they published on their website with more than 30% unused area ).

For a 400 GH/s ASIC, we are talking about:
200 cores @ 2 GHz -> 100 mm2 die (probably to high supply voltage required to meet power constraints)
400 cores @ 1 GHz -> 200 mm2 die (most feasible solution)
800 cores @ 500 MHz -> 400 mm2 die (would be the complete reticle size)

I don't say, that such an implementation is impossible. But it's is extremely risky and the thermal and power issue will be the hell. And based on what they have shown so far, I would say they are far away from tape-out.

The only thing which confuses me a bit is that Uniquify LOI. Why should Uniquify risk its reputation with false statements?
But maybe they just don't care about it, because the Bitcoin ASIC business always will be low volume and not that important for them.