Re: [LABCOIN] IPO [BTCT.CO] - Details/FAQ and Discussion (ASIC dev/sales/mining)
So the questions should be:
1) Are your first run ASICs in production?
2) How many wafers?
3) How many chips are you expecting to get out of the first run? (at some point someone said about 1-1.5k, but it would take 10x to get to 30Thash)
Also, if you're confident in your chip design, are you sure it's a good idea to wait until your first run is finished before ordering a second run? If the difficulty keeps rising at the rate it is, getting 480Thash/s a month and a half earlier could have a huge impact on profitability.
And they have a pin-out for the chip as well, which will use serial IO:
1) Are your first run ASICs in production?
2) How many wafers?
3) How many chips are you expecting to get out of the first run? (at some point someone said about 1-1.5k, but it would take 10x to get to 30Thash)
Also, if you're confident in your chip design, are you sure it's a good idea to wait until your first run is finished before ordering a second run? If the difficulty keeps rising at the rate it is, getting 480Thash/s a month and a half earlier could have a huge impact on profitability.
Example of detailed chip specs:
They won't have exact specs until after the chip if finished and tested. However, their website does list the old expected specs at 180nm:
Quote
Avalon chip
Technology Summary:
TSMC 0.11- micron G process
5 Metal
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 256+ MHz
Number of Pads: 48
8 Data
40+1 Power
Package Type: QFN48 -0.5 Pitch
Packaged Chip Size: 7 mm x 7 mm
Chip Interface
Data Pins (8 in total):
Clock i
Serial Data In [2] i
Serial Data Out [2] o
Serial Data Bypass [2] o
Reserved [1] -
Chip power efficienty: 6.6W/GHs @ 1.15 V
Technology Summary:
TSMC 0.11- micron G process
5 Metal
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 256+ MHz
Number of Pads: 48
8 Data
40+1 Power
Package Type: QFN48 -0.5 Pitch
Packaged Chip Size: 7 mm x 7 mm
Chip Interface
Data Pins (8 in total):
Clock i
Serial Data In [2] i
Serial Data Out [2] o
Serial Data Bypass [2] o
Reserved [1] -
Chip power efficienty: 6.6W/GHs @ 1.15 V
They won't have exact specs until after the chip if finished and tested. However, their website does list the old expected specs at 180nm:
Quote
Feature size : 180nm
Core voltage : 1.8V
I/O voltage : 3.3V
Core Frequency: 250 Mhz - vdd 1.8~1.85V
Number of Pads : 44
Package : LQFP or equivalent
Chip size : 5mm x 5mm
Power consumption (variable) : 1.4~1.8W
Hashing power (variable): 220~280 MH/second
I/O interface : USB / Serial
Estimated tape-out : Within the first half of July
Core voltage : 1.8V
I/O voltage : 3.3V
Core Frequency: 250 Mhz - vdd 1.8~1.85V
Number of Pads : 44
Package : LQFP or equivalent
Chip size : 5mm x 5mm
Power consumption (variable) : 1.4~1.8W
Hashing power (variable): 220~280 MH/second
I/O interface : USB / Serial
Estimated tape-out : Within the first half of July
And they have a pin-out for the chip as well, which will use serial IO:
Quote