Can somebody explain to me the suggestion that a "28nm ASIC" is basically just a 28nm FPGA... I read the eASIC press release to mean they've simplified the process of designing ASIC's to a level on par (in simplicity terms) to coding an FPGA? In other words "We've got software which basically designs the ASIC for us, based on an algorithm" rather than "our 28nm asic's are actually fpga's"
Maybe I'm missing the point here, but a 28nm ASIC is an ASIC... There's absolutely no way anyone could get 16GH on an FPGA chip, or even a semi-FPGA chip (whatever that is). If we compare the "real 65nm ASIC" produced by BFL, at 4.5GH, with the apparently "not real 28nm ASIC" running at 16GH, by your suggestion the concept that a 28nm chip can hash at 16GH is impossible.
I'll freely admit I'm not an engineer, but I am a logical person, I code, and I understand the concepts and differences between FPGA's and ASIC's. What's being suggested simply doesn't compute.
I am not an electrical engineer, and wish I could supply a proof positive answer. Fear not, I have an inquiry out seeking answers to those questions.
I understood the basic "i see it as an ASIC written in a high-level language, with plenty of deadwood code & sub-optimal layout, as opposed to being hand-coded in machine language. ROM Basic vs x86 asm" answer offered by SamuelSG - It makes a lot of sense. I also don't imagine the difference with nextream chips and cell based chips will be huge, rather maybe a 20% power consumption reduction or something. And who knows, it might be in the ActiveMining long term plan to move to cell based asic's eventually. Regardless getting to market rapidly is by far the most pressing priority, and ActiveM is well within power consumption requirements to be competitive, if not ahead of them.