That's insane. If something is wrong they will not know if it's a problem with the ASIC or not. They can't complain to the ASIC vendor either and they will not have a clue in terms of yield. Did they do this to save time so they would not have to learn and run ATPG tools?
What are you talking about? What would be an example defect that would completely disable a chip with 4 non-overlapping/non-intersecting clock trees?
A stuck at fault in the control logic or in the IO interface.