The top part of the figure has some control logic connecting the FPGA to the hashing cores to exchange data/midstace/nonce or whatever. Without access to the netlist it's not possible to analyze the probability of a single point of failure. I've seen cases of redundant logic which turned out to share some gates. Test tools can analyse your netlist and detect such potential failures. There are four different clock domains so there might be some synchronization logic in there, unless there are four separate channels with separate clock outputs, or an embedded clock. Again without access to the design one can only speculate. I can't see why KnC chose to skip this common design practice, even though a hasher itself is similar in nature to many BIST implementations even tough the signature checker will be on the device itself so I can be checked on the tester. It would have been better to do the testing on the chip tester and not struggle to figure out if the cause  of the reduced hashing capacity is due to the ASIC chip itself or some other part of the miner. And you don't need to kill all four regions to reduce the capacity of the miner. If the yield is low it will be hard to prove to the vendor that this is due to the ASIC's and not something else.