Due to double node jump, the max power should be 0.77W/GH (3.1W/GH divided by 4). Based on everything we know from any chip industry (FPGA, CPU, GPU, etc), that should be the ceiling in power-consumption.
Hi Nasser,
Brave of you to dive into the BCT feeding frenzy!
I'm curious about your numbers - 0.77 * 600 = 462W - how come it says 350W on the website?
What he is saying is that just the theoretical power efficiency increase alone gained from 55nm to 28nm should guarantee 0.77 W/GH. But he also said they improved the design (maybe fewer transistors, a "sea-of-hasher" design like bitfury, etc), therefore it should be even lower than 0.77 W/GH.
There's no way that's true. Check out this paper:
Power Consumption in CMOS VLSI chipsIt mostly comes down to the gate capacitance. I'm not an IC engineer, but my understanding (Which I'm not certain of) is that when you have a closed transistor with a +V on one side an -V on the other, then the charges on the two sides end up being like an incredibly tiny capacitor. So, even though the transistor is in the 'off' state current will still flow a tiny bit just like how it can flow through an un-charged capacitor.
And the thing is as feature sizes get smaller and smaller, the ratio between surface area and volume goes up, and the gap between the gate and drain get smaller as well. And of course you have more transistors.
And I also think gate leakage is higher with smaller nodes as well.
On the other hand, the voltage can be a lot lower.
Either way, claiming you'll have a straight linear relationship between feature area and power seems kind of ridiculous to me. I guess we'll see.