I stop you right there. Bitfury has a chip consuming 0.8 W/Gh/s and it is 55nm. So it is beyond any doubt that a 28nm chip (theoretically 4x more efficient) can increase efficiency to at least 0.77 W/Gh/s (which necessitates only a 1.04x improvement).
I'm not doubting 350W for 600Gh. But, there is a huge difference between a new, efficient chip and simply doing a die shrink on BFL's horribly designed power-hogs.
BFL's are Jalapenos 6W/h Avalon's at 110m are about 9W when overclocked. So clearly the chip design plays a huge role in power use. It's not directly related to feature size like that.
Yes BFL's design is horribly inefficient. But no matter whether the design is good or bad, there basically
is a straight relationship between feature area and power. This is true for large process nodes. This is less true for smaller ones (such as 28nm) where leakage becomes relatively more important as you pointed out.
So let's be pessimistic and let's assume that leakage causes a 50% increase in power consumption (1.5x), and let's assume BFL manages to merely decrease power consumption by 10% on paper by tweaking the digital design (0.9x), then:
3.1 (W/Gh/s at 65nm) * (28/65)^2 (theoretical efficiency improvement from 65nm down to 28nm) * 1.5 * 0.9 =
0.78 W/Gh/sThis is all back-of-the-napkin math, but again I don't see why 0.77 W/Gh/s looks undoable, even taking into account BFL's current horribly inefficient design.