Re: [LABCOIN] IPO [BTCT.CO] - Details/FAQ and Discussion (ASIC dev/sales/mining)
I guess its fair to say that I'm a bit nervous about Labcoin; a result of having a lot invested and not getting any of the fundamental questions answered..
Did anyone figure out an explanation/theory to the following already? Quoting from the somewhat dated http://www.labcoin.com/presentation.html page, the initial road map was to have a 180nm chip with estimated ~250Mhash performance ready in August/September, and their second generation chip of 65nm at estimated 4-5 ghash at a later date... And from that they went to 130nm but with the same hash speed they targeted for the second generation chip?
I guess my gut feeling tells me that the chips will not perform even close to the 4ghash performance announced, however, it might still be profitable.. just not as profitable as projected..
Did anyone figure out an explanation/theory to the following already? Quoting from the somewhat dated http://www.labcoin.com/presentation.html page, the initial road map was to have a 180nm chip with estimated ~250Mhash performance ready in August/September, and their second generation chip of 65nm at estimated 4-5 ghash at a later date... And from that they went to 130nm but with the same hash speed they targeted for the second generation chip?
I guess my gut feeling tells me that the chips will not perform even close to the 4ghash performance announced, however, it might still be profitable.. just not as profitable as projected..
Quote from: http://www.labcoin.com/presentation.html
The technology, version 1
Specifications:
Feature size : 180nm
Core voltage : 1.8V
I/O voltage : 3.3V
Core Frequency: 250 Mhz - vdd 1.8~1.85V
Number of Pads : 44
Package : LQFP or equivalent
Chip size : 5mm x 5mm
Power consumption (variable) : 1.4~1.8W
Hashing power (variable): 220~280 MH/second
I/O interface : USB / Serial
Estimated tape-out : Within the first half of July
Specifications:
Feature size : 180nm
Core voltage : 1.8V
I/O voltage : 3.3V
Core Frequency: 250 Mhz - vdd 1.8~1.85V
Number of Pads : 44
Package : LQFP or equivalent
Chip size : 5mm x 5mm
Power consumption (variable) : 1.4~1.8W
Hashing power (variable): 220~280 MH/second
I/O interface : USB / Serial
Estimated tape-out : Within the first half of July
That data is out of date, they're doing 130nm, not 180.
LOL, nice one Ytterbium... You clearly didn't bother reading my post at all....
This isn't an endorsement but I think you are worried about the wrong thing.
Bitcoin is an "embarrassingly parallel" problem (google it). The specs you cited contained no die size. Even if there was no change in the hashing engine design, the 180nm design could have consisted of 1 hashing engine per chip (@ 250 MH/s nominal) and the 130nm design consist of 16 hashing engines (16*250MH/s nominal) per chip. Obviously the die size would be 8x larger (16*(130/180)^2) and use more power but without more details like die size, estimate marginal cost, and power consumption of both the 180nm & 130nm it is not possible to draw any conclusions on the realism of the specs.