If my suspicion about the labels being reversed is correct, and 32AW is a multiplier for FAW, then 6/8 is perfectly fine. FAW would be 6*RRD, and 32AW would be 8*6*RRD.
That also would better explain the observation that setting what they think is 32AW to zero causes instability.
As for the tool I'm working on, you can get an idea of how it works by looking at my fork of amdmeminfo.
https://github.com/nerdralph/amdmeminfoI modified it to show runtime strap values. My tool doesn't just read them, it writes them too.
I believe Yurio is ahead of me in this process with his Windows miner now being able to do runtime timing modifications.
https://github.com/zawawawa/GatelessGateSharpThat formula seems wrong, or i am missing something.
Elpida is as follow:
1500: 6/10/7
1625: 7/12/8
1750: 7/12/8
2000: 7/12/8
No matter how you put it, neither tFAW and tFAW32 can be any multiple of tRRD.
Currently using tFAW = 0 and tFAW32 = 4.
For what i remember actually, tFAW if its set to 0, its actually read as 8. Dunno if each single value counts as 8, or if its just timing properties. If its the first - that would make sense for the 1625-2000Mhz straps. That makes possible the following : tFAW = 7 * 8, Which would also fall in line with what you said.
I said, "32AW is a multiplier for FAW", not a "multiple of". So programming memory controller to use 8 for 32AW means 8*FAW, and a value of 6 for FAW means 6*RRD.
Using anything lower than 8 for 32AW should be irrelevant, as should using anything lower than 4 for FAW.
Another complication in finding optimal timings is that they vary slightly according to the memory controller characteristics. Newer GPUs like Tonga and Polaris have improved memory controllers, likely with deeper queues, which allows more memory accesses to be grouped together in the same bank, reducing the impact of FAW & 32AW. These newer cards tend to benefit from slightly looser timing (CAS, RRD & FAW) with a higher memory clock. Older GPUs like Pitcairn seem to be better with a slightly lower memory clock but tighter timing.