Sorry first portion got chopped off.  I fixed it.

The ones in parenthesis are called half nodes.  In the early days there was just one standardized sets of process nodes.  Each one was linearly 70% of the prior node.  Remember chips are two dimensional so if you cut the length of a gate by 30% then you will cut the area by (0.7^2) by roughly half.  So each process node roughly doubles the number of transistors per square mm.

However the time between major node jumps is at least two years and later that has been slowing down.  For products which need faster improvement cycles (namely GPU) fabs began offering half node equipment.  Also it is sometimes possible for a fab to be upgraded to the half node improvement extending the ecnonomical lifespan of the chip.  Today the use of the term "half nodes" is kinda dated because many designs (like GPUs) simply upgrade only on the half node (i.e. 40nm, 28nm, 20nm).  For all intents and purposes they are just another standardized fabrication size.

As for ASICMiner vs Avalon 110nm is a different process node than 130nm.  For a given design, in theory it will result in smaller transistors, higher clock speed, and more chips per wafer. However the improvements aren't as significant as a full node jump.  If ASICMiner used 110nm instead of 130nm everything else being the same we would expect them to have ~40% higher wafer density (130nm/110nm)^2.  Still Avalon vs ASICMiner brings up a good point.  It shows that DESIGN matters a lot.  Despite the 40% "disadvantage" ASICMiner is more than competitive with Avalon.  Nothing indicates they have higher cost, energy consumption, or lower hashing density. Bitfury (55nm) chips beating KNC (28nm) is another example.  So process node matters but it is only half the equation.

Of course given the NRE costs nobody is going to make a half node jump.  Makes much more sense for ASICMiner to jump down 1 or more full process nodes.