Personally I prefer large 16 nm FPGA. You can build almost any altcoin except ETH.
I am looking at the directed graph of operations in Cryptonight algorithm, and I don't like it. The 128 bit multiplier and AES blocks have high latency and therefore the storage of the 2 MB contexts must be done in the external memory. The good news are that logical resources are almost free and it probably possible to build dual miner Monero+nist5. Also DSP blocks are suitable to build triple mode miner XMR+nist5+some another coin. So I prefer diversification, although the top-range FPGA part could be not optimal for solo XMR mining.

I have seen the messages in the discussion of the XMR V7 POW selection. Some man advises to use high bandwidth memory with serial interfaces. I would agree, but it could be complicated and expensive solution.
Maybe HyperRAM is also usable, I like low cost and simple interface of this memory,