which leads you to believe everyone except KnC is lying through their teeth about their specs, and which leads me to question if KnC are doing a full custom design.
btw, VMC is doing a structured ASIC and their efficiency projections are better than KnCs. OF course they may also be overly optimistic, but still.
Besides, you havent explained the die size.
28nm standard cell, is a 28nm standard cell, either you realise this now, or time will demonstrate this fact.
How exactly would you tell?
And how do you explain the picture of the PCB with a cyclone FPGA that was used to test the board? What are the odds a full custom asic would end up with the exact same compatible pinout as a cyclone/hardcopy?God you're dumb. Full custom isn't the same as standard cell. And obviously you can create a digital logic ASIC that will be pin-compatible with an FPGA.