What's the usage of Vref?
Could you verify that all SPI pins are signaling at 1.8V, please?
Which pin is supplying the 1.8V input?
Have you decided which rail is GND yet?
Edit-1: Or are both rails supplying the internal voltage, and the only GND is the central pad?
Edit-2: I hope both rails aren't Vinternal, since that would force either a 4-layer board, or high inductance breaks in either the cooling GND plane or the Vinternal plane. There is a reason that prior chips didn't use a plugged-tunnel approach to pinout...
P.S: a link to the github location of these specs would fulfill one of your previous promises....
Thanks!