Well I bit the bullet and tweaked the 0x86 register on one die. I tried a few different values, 0x0168, 0x0068, and 0x01ff. initc did not seem to throw any errors, and everything hashed like normal. I did not notice a difference in power consumption on any of the settings, so I can only assume the hash clock was not affected.
So ... there goes that theory.
Awesome job figuring out that checksum algorithm.
Take a look in /etc/init.d/cgminer.sh and you will have your answer to why nothing changed.
It is writing to the same SPI PLL registers by hand in there just before starting cgminer, not looking in the eeprom.
for p in $good_ports ; do
# Re-enable PLL
i2cset -y 2 0x71 1 $((p+1))
for c in 0 1 2 3 ; do
cmd=$(printf "0x84,0x%02X,0,0" $c)
spi-test -s 50000 -OHC -D /dev/spidev1.0 $cmd >/dev/null
cmd=$(printf "0x86,0x%02X,0x01,0xD1" $c)
spi-test -s 50000 -OHC -D /dev/spidev1.0 $cmd >/dev/null
cmd=$(printf "0x85,0x%02X,0,0" $c)
spi-test -s 50000 -OHC -D /dev/spidev1.0 $cmd >/dev/null
done
The table for disabled cores is also stored in the eeprom at offset 0x4c and 192 bits forward.