Folks, in your paragraph 1.1, General protocol specifications, you write:

"The CoinCraft A1 uses two SPI ports, one used in slave mode as an input from the uC or
the previous A1 in the chain (pins IN_MOSI, IN_MISO, IN_SCLK, IN_CS) and one in
master mode to the next A1 in the chain (pins OUT_MOSI, OUT_MISO, OUT_SCLK,
OUT_CS), if any."

In your pin descriptions, you use completely different signal names.

http://i.imgur.com/IXQavZw.png
http://i.imgur.com/tRFsGLK.png

It seems reasonable to assume that the above mentioned slave port, meant to be connected to the MCU or a preceding A1 consists of:

Signal	Pin	Input to A1?
SCK_S	13	input
SDI_S	14	input
SDO_S	15	output
CS_I	16	input

and the above mentioned Master port, meant to drive subsequent A1s consists of:

Signal	Pin	Input to A1?
SCK_M	8	output
SDI_M	7	output
SDO_M	6	input
CS_O	4	output

and that SPI signal flow outbound from the MCU will travel from right to left when looking down on a board with "pin" 1 in the upper left corner.

Could you please verify that I have the layout correctly described, please?

In addition, could you please verify the polarity of the chip select signals? Chip select is only rarely active high, and my controller is wired for the usual active low chip selects...
I would prefer not to rework the prototype boards I am submitting due to my misunderstanding...

Thanks!
--DickMS