That was my plan with the CPLD - 1.8v I/O within each board, 3.3v between them and the controller board.

Unfortunately I didn't think through the implications of powering the rpi independently of the 3.3v to the board during bring up - I wanted to be able to measure the board's 3.3v draw. Unfortunately if you power the rpi up before the board, you send 3.3v into an unpowered I/O pin on the CPLD and the chip goes into latchup

I would have liked to have c-scape in my design review to say 'you don't want to do it like that!'