In our under development design, I use a 45A rated, 55A stable, 60A peak DC-DC circuit for 14 chips. I do think this is a good start.

Basic configuration is 7 chips pre bank, 2 banks share one DC-DC. Will open-source when the test is over.

By different operation voltage and clock speed, the chips power consumption is vary greatly. for example, 1GH@0.8V only consume <1.5W, about 1.9Amps. 1.5GH@1V is about 3.75W, about 3.75Amps. There is no doubt this chip can over clock to 2GH (this is limited by PLL at 25MHz XCLK input), but the voltage must increase to maybe 1.1V (NOT tested),  the overall power consumption may increase to 6W and 5.5 Amps.

So, select which DC-DC module is depend on which type of product you want. more power efficient or push the chips to its limit?

By personal views, A3255 chip is cheap, if over clock too much will go with a huge increase of peripheral (DCDC, heat dissipation, etc)cost, then it's unworthy. just add a few chips and run under lower voltage. In other words, this is an art of balancing.

In addition, use Ti power module is a good solution for fast shipping, but they are really costy. I will release a opensourced 2 phase 55A DC-DC design for reference next month(sorry, it's a bit slow but high-current DC-DC circuit is not easy to design and debug), it' maybe only cost 5$.