Post
Topic
Board Development & Technical Discussion
Re: Modular FPGA Miner Hardware Design Development
by
Olaf.Mandel
on 14/07/2011, 20:15:57 UTC
[...]
So long as you stick to only reprogramming these USB AVRs via the factory-preprogrammed USB bootloader, I don't think you can brick them. Which is fortunate, because recovering from a disabled RESET pin is apparently a pain; it requires a high-voltage parallel

In a weaker version of that sense, the MSP430 is also "unbrickable": as long as you don't touch the default BSL and as long as your code leaves the write-protect alone, everything is fine. The problem is that an inexperienced user (or someone who types command-lines on autopilot) may easily reflash the BSL.

[...]
Yeah, it just makes doing I/O interfacing a tad more tricky. As Olaf said, most of the FPGAs we're likely to use can run at 3.3V for I/O anyway, and if necessary level shifters are an option. (Looking at the Kintex-7 data sheets those support 3.3V on a subset of the I/O pins too.)

Actually, you shifted what I wanted to say where a bit: I meant that while the current FPGA can do 3.3V, I am not sure how many others can do so.

And having to use level shifters is very annoying. I just looked, though: the MSP430F5528 (and comparable chips) has several banks of GPIOs, but there is only a single supply voltage for IOs. And if you use 2.5V for the FPGA connections, you cannot use 3.3V for the connections to the DIMM bus (except for the USB, of course).