PCIe, even 4.0 for which backplanes are not yet available, is 8 or 16Gbps per transceiver vs 28 Gbps in the QSFP28s
I wasnt referring to 1525s though, I was speaking about other boards with 56+ transceivers exposed.
OK, so both Xilinx and Bittware boards have 16 xcvrs hooked to PCIe edge connector
...
Or maybe you just thought about PCIe 4.0
motherboards instead of
passive backplanes?
I was thinking PCIe spec backplanes, but I see what youre referring to. I would be surprised if the edge connectors electromechanical could support higher than 16 per transceiver, theyre a pretty loose fit. Ive seen how much engineering goes into things like sea-ray connectors but as you said BER may remain acceptable for losses crypto mining. I also forgot PCIe is bi-directional as well, so 16 TX + 16 RX pairs as much as ~400Gbps each way in a ring. still 1/16th of what would be available with a dedicated 128 transceiver design, and those parts are in the ballpark of a VCU1525 in quantity. Take a look at some of the ASIC verification setups based on 4+ VUP parts. HTG I believe has some.