Hmmm, two accelerator cards will be daisy chained with pipelining and their performance will magically double. I will believe it when I see it like all other claims made by the OP.
Why it wouldn't pipeline efficiently? There are 8 transceivers available over QSFP28 that work at the raw speed of 32.75 Gbps for a total of 262 Gbps from one board to the other in one direction. No back-channel is required, also we don't care about protocols and error detection & correction over our link, it is for lottery purposes only.
If that is not enough there are 16 of the same transceivers connected to the PCIe edge connector. This may be a little more tricky, to run them at full blast without obeying PCIe protocols we would need to either do some simple trace cuts on the backplane or find a way to busy-out and/or disable the PCIe bridge chip.
I seriously don't see the inter-board bandwidth as an important limitation. I haven't done the above with the Ultrascale+ technology, but I've successfully found ways to abuse the older connectivity standards (for an application not related to cryptocoins, but also tolerating occasional noise.)