Seems thats what i get for writing to long posts. 
All in all: we should probably finalize PCB specs (see below), so people can do the FPGA routing. This is nearly independent of the interface logic and power supply, but changing the specifications means having to redo a lot of the work. I would like to know:
I registered with pcbcart now, and my concerns about min wire thickness and distance are put to rest: you can specify many different combinations. Also: their 4-layer is nearly as cheap as the 2-layer board, so there is not much point going two-layer (I was used to having to pay much more for 4-layer boards because of the extra manufacturing steps).
But can someone answer me these questions:
But can someone answer me these questions:
- What is the pcbcart default layer stack? Alternatively: what is a good layer stack we should specify?
- What does pcbcart mean when they ask for the "Min. Annular Ring"? The width of the ring on one side ((D_via-D_hole)/2) or the sum of the width on both sides of the hole (D_via-D_hole)? -> annular ring specifys a radius measure so annular ring(0,2mm)+drill radius(0.1mm) results in a minimum total diameter of 0.6mm, objections ?
- What does "Impedance Control" mean in this context? A better selection of the board stock?
- I went with the "Lead Free HASL - RoHS" surface finish. Other suggestions? -> I was told Gold finish is suited better for BGA it would increase the total price by 15$
- Do you want to order the prototype from there, too? The minimum lead time of 12 working days plus shipping time translates to waiting three weeks for the board.-> you have got a point there, but i prefere the unbeatable price and industry quality over a quick delivery
All in all: we should probably finalize PCB specs (see below), so people can do the FPGA routing. This is nearly independent of the interface logic and power supply, but changing the specifications means having to redo a lot of the work. I would like to know:
- # of layers -> 4 to minimize board size
- thickness of copper for each layer -> im not an expert on this but ground and 1.2V will need 70um or more to allow narrow lines
- min trace width -> in acordance with the pcbcart requirements 0,2mm
- min space between things -> in acordance with the pcbcart requirements 0,2mm, might be reduced if needed for wiring between the FPGA pins
- min drill size -> in acordance with the pcbcart requirements 0,2mm
- min annulus -> in acordance with the pcbcart requirements 0,2mm