For example - there are 40 pins that provide IOVDD and IOVSS - do you really have to have 40 pins for that? Do they have to deal with that high currents?
Well, they do need quite some lines I think... Rough estimation is that @0.85V and 0.5W/Ghs they would need to have ~59 amps (100ghs*.5W / 0.85V) per chip (not including losses and such and assuming 1 chip per 100ghs device).
And the other question - heat - what are the plans to deal with that?
Is the silicon going to be exposed (BFL-like) where users can attach a proper heatsink? Or is heat going to be dissipated through the PCB? If the second then bitfury-like packaging with a huge pad underneath the chip (and tons of vias on the pcb) will be better than a bunch of balls/pins.
Yes, heat is going to be substantial, but 50W is not too crazy for a chip with a large heatsink. Pictures of testing heatsinks have been posted as Carlton is mentioning.