I really have no news to share, but want at least to forward Bitmine's information that everything is still on track.
OK so if everything is still on track where is documentation reference design and programming? There should be published for 29 days at lest... Even if chip is on time that will not help us without having boards ready...
EDIT: I would definitely be interested but with BFL experience that I had(change from sample to production chips)... I really don't know with current data what can be done till I see more data...
I am unfortunately only SW-engineer and from my limited understanding of the HW side I got that (among others) the WASP team was in direct contact with Bitmine and clarified remaining issues. With that, IIRC a revised spec was released that the teams found sufficient enough to design with. If that is not the case, please let me know or post open topics here.
As for the reference design, I remember there is a design contest planned, but it seems Bitmine is too busy with development to announce it in time. I will check status and report back.
What I for sure am committing to (and agreed with Bitmine already) is to cover the SW side of this project. Bitmine will be visiting Innosilicon next week and plans are to grant me access to the FPGA-based chip emulator, so I can work on test and mining SW. With that, there will be a cgminer driver available before first boards are assembled.
I started this thread for the DIY chip distribution only, but somehow it was nominated as the official technical support thread for OpenSource designs. While I am fine with acting as proxy between you and the overloaded Bitmine crew, I myself have been busy over the past 4 weeks and therefore limited to care way less than I would have liked. It is not too late yet, therefore please feel free to demand for what is missing and make this a successful community project.