It's worse than that: we want to be able to bring down the FPGAs deliberately if they are drawing too much power. How much data would need to be moved across the bus every time we do this? So far the assumption is that bandwidth is negligable. Edit: 1.6MB can take minutes at standard serial speeds.
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This is not quite right: the bandwidth needed for mining is negligible. The bandwidth available through either of the two interfaces still in the designs (JTAG and SPI) is much higher. Assuming 2MHz clockrate on SPI (the default value in master mode), we need 17s to bootload the FPGA. As the FPGAs have the same bitstream, they can be loaded in parallel. For a higher clock speed we are faster, e.g. for 33MHz we need only 1s.