The bandwidth between the two FPGA's is 320GBps which supports the 512 bit intermediate result x 625MHz, so the hash rate of two FPGA's connected does not suffer from the interconnect.
Its true for theoretical bandwidth in datasheet. Yes, but not in real implementation. Even if you have a 320GBps between FPGA you can reach only 320 000 / 512 = 625 MHash/sec. But in real project it will have additional speed lost in input/output part.