FPGA Power considerations
Spartan 6 FPGA Power Management
http://www.xilinx.com/support/documentation/user_guides/ug394.pdfThe FPGA can only enter suspend mode if enabled in the configuration bitstream (see
Enable the Suspend Feature and Glitch Filtering, page 14). The SUSPEND pin must be Low
during power up and configuration. Once enabled through the bitstream, and the
SUSPEND_SYNC primitive is not present in the design, when the SUSPEND pin is
asserted, the FPGA unconditionally and quickly enters suspend mode.
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There are four possible ways to exit suspend mode in a powered system:
Drive the SUSPEND input Low, exiting suspend mode.
If multi-pin wake-up mode is enabled, drive the SUSPEND input Low and then assert
any one of the user enabled SCP pins.
Pulse the PROGRAM_B input Low to reset the FPGA and cause the FPGA to
reprogram.
Power cycle the FPGA, causing the FPGA to reprogram.
sounds pretty simple to put this guy into suspend, and it will retain it's programming in that state too, and all that's needed is to enable it in the bitstream and to assert the SUSPEND pin when you want it to go to sleep. Sounds like you guys want to tie that to the MCP so then it can control if the FPGA is on or not.
there is also a hibernate mode, but it basically just sounds like a way to safer way to power up/down in hot-swapping situations
What is the configuration consensus again? Bit banging the MCP's I/O and a JTAG chain of the 2 FPGAs?
it also says:
Saving Power
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The lowest power state is the quiescent state with no inputs toggling, all outputs disabled,
and no pull-up or pull-down resistors in use.