...but the rule I'm talking about - is GENERAL, for devices using transistors 
For FPGA, the power scales linearly with clock.
https://www.researchgate.net/figure/Dynamic-power-consumption-vs-processor-clock-rate-measured-on-Spartan-3-FPGA-The-number_fig7_258762660
Power in a circuit scales linearly with clock speed and exponentially with voltage.
P = capacitance * voltage^2 * frequency
The reason why thermals spiral out of control at high clock speeds is because you also have to keep cranking up the voltage to keep things stable as the clocks go up.
I didn't think this is different for FPGA. Is it?
If that holds true, dropping the voltage on the FPGA to 0.75V from default 0.85V will allow for about 125% of baseline unmodified performance by allowing 25% OC within the same thermal envelope, assuming it is stable. So maybe about 11GH/s per card.