I think this smells like scam, I can't find the google page right now, but some of that last press releases was pretty much lifted from a textbook talking about a SHA core implementation based on a Pilchard design - or mebe that was the Pilchard design.  Even the things like polling communication.  If it helps anyone, I was googling for Pilchard, and I ended up on a google books page, but after reading the section that came up, it literally was almost word for word the same as their latest news description.

On the other hand.  There are "ASIC"s out there that are literally just stripped down FPGAs.  For example, you can design something on a Xilinx FPGA, and then you once your design is set in stone, you can actually send it off to Xilinx to make "ASIC"s from that FPGA design.  It's basically just a FPGA without the FP ( Field Programmable Gate Array => Gate Array ).  And it's not as cheap as a real ASIC, but it's definitely cheaper than an FPGA - per unit price.  Xilinx also expects volumes in the thousands if not millions to even provide the service.  But I could see cheaper Chinese companies doing this type of thing.  So I don't think it's out of this world to think that it's not an "ASIC" in this term of the definition.

Now back again to the scam side.  480-500 MHash/s just sounds unfathomable for what I just described above.  To obtain these types of hash rates you would need either multiple SHA cores running in parallel ( AND pipelined, i just don't see enough cores getting packed in ), or one core running at extrememly fast clock rates.  I just don't see either of these happening in an FPGA type ASIC.  I would expect maybe something on the order of 100-300 MHash.  As said earlier, you can't really do much to optimize the math/logic that goes on in the alogirhtm.

I also find it funny that they think using some sort of external memory could possibly be faster than using the on-chip BRAMs.  Or if they are using the internal BRAMs, then how they could possibly think that doing something like this could get them anywhere near such an efficiency boost in terms of clocking.  The critical path in the SHA logic is not constant inputs - it's the adders - 32-bit adders that need to execute in one clock means you have a 32-bit carry chain to deal with, and I would likely assume that is going to be the critical path here - 32-bit adder carry chains with inputs that need to be xor'd.

From little information he has provided, IMO just seems fake and I hate to say it, but very chinese.  I love his reactions in that reddit thread - people criticize the legitimacy and retorts with "FINE MAYBE WE SHOULDN'T GIVE YOU ANY INFORMATION" - LO-fucking-L.  I don't know who is still interested in this vaporware, but it's definitely got me not interested - who wouldn't want to deal with someone like this?

I'm not even sure if photos/videos of this thing "working" will cut it at this point.  Maybe if it was a spur of the moment - someone asks for a pic/video of this thing running, and 5 minutes later these guys post a response because they actually have it running live.  But the way it is now, I'd expect any further "proof" to be highly constructed/photoshopped/faked.  How is he even supposed to "proove" he has one of these things up and running?  It's like an iphone jailbreak video - it's a freaking video, it's so easy to fake that shit - it's so easy to shoot it 100 times till you stop making a mistake.  It's like one of those japanese video magicians....

I don't know, but at least in my mind or someone prooves me wrong with some real solid proof - this just screams scammer to me.

Here are some questions I would ask and expect to be answered with out giving away the technical details of the implementation of the design.

What is the core clock rate of the chip?  How many SHA engines are running?  How many clocks for each core to produce a hash?  Are they fully pipelined?