Post
Topic
Board Mining (Altcoins)
Re: Dwarf FPGA – the anti-ASIC
by
melpheos
on 06/06/2018, 07:50:18 UTC

--To hide the soldering path...But once the unit is released (if it is released) everything will be know so I don't see the point
The time for reverse design will be lost. We will release a new version earlier than the old version will be copyed.


New version ?