Re: [CPU] JCE Miner Cryptonight/forks, brand new, super fast!
When I try the latest version on an AMD Epyc (basically four Ryzen dice on a package) I get the following error:
Thread 30 successfully bound to CPU 30
Allocated 2MB Cached Large Page Scratchpad Buffer for CPU 30 of NUMA node 3 at: 0000021b3c200000
Starting CPU Mining thread 31, affinity: CPU 31
Thread 31 successfully bound to CPU 31
GetNumaProcessorNode failed for cpu 32, error code: 87
Retrying with no NUMA
Allocated 2MB Cached Large Page Scratchpad Buffer at: 0000021b3c400000
Connecting to mining pool support.ipbc.io:17777 ...
Devfee is 1.5%
That's strange because I only defined threads for the CPUs 0 to 31 in the config file.
Why does the miner try to access a CPU (core) 32, which is not present? Apart from that the miner starts mining and has better hashrate than XMR-stak with Bittube: 5200 H/s vs 4900 H/s. 
In wikipedia no info about L1/L2 cache on Epyc. Only L3. Does L1/L2 cache exists on it or not? Just interesting...Thread 30 successfully bound to CPU 30
Allocated 2MB Cached Large Page Scratchpad Buffer for CPU 30 of NUMA node 3 at: 0000021b3c200000
Starting CPU Mining thread 31, affinity: CPU 31
Thread 31 successfully bound to CPU 31
GetNumaProcessorNode failed for cpu 32, error code: 87
Retrying with no NUMA
Allocated 2MB Cached Large Page Scratchpad Buffer at: 0000021b3c400000
Connecting to mining pool support.ipbc.io:17777 ...
Devfee is 1.5%
That's strange because I only defined threads for the CPUs 0 to 31 in the config file.
Why does the miner try to access a CPU (core) 32, which is not present? Apart from that the miner starts mining and has better hashrate than XMR-stak with Bittube: 5200 H/s vs 4900 H/s. P.S. 2Mb L3 cache per thread allready too low... AMD can add more L3 cache on Epyc... Especcially if L1/L2 cache is absent...
L1 -> Level 1
L2 -> Level 2
L3 -> Level 3
as the levels get higher, the cache is slower but larger. Maybe AMD is using some clever technique so L1/L2 caches are more shared than they are already, so mentioning it is useless. But absend L1 or L2 cache would have a huge impact on performance.
I just look in wiki and there no info about L1/L2 on Epyc... Just stays "N\A"...
Not sure which Wikipedia you are looking at, but on https://en.wikipedia.org/wiki/Epyc you can see L2 cache
or even better, on https://en.wikichip.org/wiki/amd/epyc you have even more information
And if you use logic, there is no way a cpu will have L3 cache and not have L2/L1, since in that case L3 becomes L1...