Post
Topic
Board Development & Technical Discussion
Re: Modular FPGA Miner Hardware Design Development
by
Olaf.Mandel
on 31/07/2011, 21:17:05 UTC
I just read through the MSP430 docu and found two things:

Good news: multiple SSEL signals are no problem. The STE signals provided by the serial engine are different from the SSEL signals. They are to facilitate multiple masters on one bus, so we don't need them. This means we can set UCMODEx=00 (3-wire mode) in both UCA1CTL0 and UCB1CTL0.

Bad news: the way the two serial engines are multiplexed onto the output pins, it is impossible to configure one engine to 4-wire mode and use the second engine at the same time. We don't need to to that, but this raises the question if two concurrent 3-wire SPI engines on the same port are even possible at all. Can anyone who knows their MSP430 forward and backward answer this? Alternatively we could use a 64-pin package (the 5510IRGC).