So basically what I'm getting from all this is, it's very time consuming releasing bitstreams for the public which makes FPGAs vulnerable to forks just like ASICs are. FPGA can't compete with ASICs and can be forked with fairly good success since developers working on bitstreams is scarce..
As a miner you're basically a sitting duck twiddling your thumbs hoping a bistream is released before the coin forks again.
Miners like STAK, SRB and Cast (for gpus) can release new revisions with new algos within hours of a fork.
Say Cryptonight V7 forks again to V8. How long would the wait time be for a updated bitstream?
This true to some extent, it certainly takes longer to develop a bitstream that to change GPU code. Ironically, the biggest reason for the difference is that it takes a PC seconds to recompile GPU software with a 5-line code change. Make the same tiny change in your verilog source code and you are looking at 25-80 hours for the tools to rebuild the bitstream and sometimes it can take 20 tries to get one that passes timing (hopefully run in parallel).
A developer who has built an extensive library of functions for previous algorithms can in many cases 'follow a fork' in a very short time. A developer who does not have access to the same library would take much longer.
Eventually as FPGA's get more popular, developers *will* have access to their own large private libraries of functions and will be able to follow forks pretty quickly, say about 7 days lag time.