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Especially for the VCCINT regulators I'd tend to stay on the positive side of the tolerance, as there will be non-neglegible voltage drops across the traces and FPGA pads. Remember that VCCINT directly affects achievable hashrate. Up to 1.26V are allowed here (1.32V absolute maximum), so I'd probably go for 1.25V for this rail if the regulator feedback comes directly from the FPGA's pads.
To take advantage of this you'll need to define the guaranteed minimum voltage in the UCF file.
I think moving the resistors below the FPGAs is a given by now. But if we increase the core voltage to achieve higher clock rates, then I would ask how close we want to cut it: is there a risk of having any EMF mess with the trace from the resistors to the switcher, so that the switcher runs at a too high voltage? What about required or suggested resistor tolerance: is 1% sufficient?
And our of curiosity: what is the gain in terms of clock rate for a voltage increase of 0.05V? I am willing to take ISE estimates after whichever stage you feel is remotely reliable.