If we're working on a DIY board for the A1, how do we get in the queue for sample chips?

I should have my design done this week.

Zefir: can you clarify the clock frequency required for the PLL. On the datasheet it quotes either 12MHz or 32MHz. Will either 12MHz or 32MHz give access to the full PLL range, or would the option of selectable external clocks in the 12-32MHz range be useful?

thanks!

-a[g