Let me put this here for you brother: your box currently does CNv1 only. XMR is forking in two days to a new version of the algo (CNv2) that is going to be 4 times slower for FPGAs.
Not OP advocate, but FPGA can be reprogrammed and these changes are not a problem to be implemented in FPGA the fact that the devs are putting the FPGAs in the same bag as ASICs makes me question their statement and its pure PR but again time will proof the only thing i can think of they are increasing the "space" requirement for the FPGA to implement the algo not the speed.
Correct. But OP claims 60 days ROI. That's a profitability metric. From that moment on he's leaning out the window and he's gotta back up his claim to potential buyers.