That would be true if you would use most of the die estate. But these wafers contain various generic circuits that can be used for all kinds of applications, and therefore are anything but optimal for any particular application. Its a halfway solution between FGPA and ASIC. THere is also the tooling cost, since these wafers are produced in two phases, most of the layers for the generic easic nextreme process, and then later one application specific layer is etched. Fabs will charge you a pretty penny for that, even if eASIC wouldnt.

Then there is the ebeam thing; chips produced through ebeam will be a whole lot more expensive, because its a time consuming operation using very expensive equipment. I figure that will only apply to the first batch though, maybe as few as one single wafer to see if the chip works, and to allow PCB development/debugging.