Post
Topic
Board Hardware
Re: Official Open Source FPGA Bitcoin Miner (Spartan-6 Now Tops Performance per $!)
by
Anoynomous
on 18/08/2011, 02:02:19 UTC
if the above solution is applied, the calculation of new_w will be the new critical path...
new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];

again s0_w can be calculated a loop ahead and added to  rx_w[31:0]. this way our new_w will be shortened to:

new_w = s1_w + rx_w[319:288] + rx_w[31:0];

dcreasing the critical path and possibly increasing the clock frequency...

Can anbody tell me the %age LUT utilized after synthesis... there may be a possibility of replacing the adders logic... Smiley