CPU like instruction counts have very little to do with designing an ASIC. ASICs are designed using an RTL language. RTL stands for register transfer level, and is totally unrelated to CPU style sequential instructions. Essentially, an ASIC design means setting up a gate pipeline that has a certain delay to produce the first output, but after that short delay the circuit spits out 1 solution every clock cycle.

It is like turning on a hose. There is a delay for the water to move from the faucet to the spout, but once water starts coming out, it comes out in a continuous stream.

Nobody does SHA256 hashing with computer like instructions. It is all fully unrolled pipelines, with as many of them crammed onto a piece of silicon as possible. It is not done as a sequential operation in the way you are thinking of it. What you need to do if you want it to be interesting to ASIC manufacturers is to come up with a way to significantly reduce the number of transistors in a fully pipelined circuit.