I believe he was saying he didn't have any extra chips. A single chip design should function just fine.
Does anyone happen to know if the reset line needs to be pulled high. It wasn't specified, but most resets are. I plan on connecting all the reset lines to a bus to a Uc through a level converter.
Actually, no. The only person who documented attempting a single-chip design is having issues with the SPI chain termination. We don't actually know if single-chip works yet.
Data sheet says "Reset signal, active low"