OK, I'm now mining on an Altera FPGA with poclbm. (Well, some heavily hacked-together Python code based on poclbm to be exact.) You can find the code in question on Git here but it's a bit of a pain to use right now; you have to create a new BSDL directory, obtain the BSDL file for the FPGA you're using and copy it to the directory, edit the source to use the correct directory, and then run it and hope it finds the correct USB Blaster and works. Oh, and it needs UrJTAG installed.

In theory this means that you can now mine using fpgaminer's code for Altera FPGAs that communicates over JTAG without having any Altera software installed. (It also has long polling support obviously.)

Edit: Now has a bsdl/ directory in the source tree to place the bsdl files in.