So I'm in the final stages of PCB layout here (hoping to release the board today or tomorrow). Still one question is pending however: are there any sequencing restrictions on bringing up the IO/analog and core voltage supplies for the A1? I'm currently planning to bring up IO, then the core supply - will this be ok?
I've asked Bitmine as well and the question has been forwarded to engineers but no reply as yet.
There are no related restrictions documented or known and I am not aware that anyone from the working designs is keeping some defined bring-up order. The only requirement documented is the reset sequence (1s low, then 1s high before first command is sent).