RISC-V ISA has implemented and was developed using FPGA's. These devices are used for testing gates before taping it out as an ASIC (CPU is a programmable ASIC) .
Well these devices have several GPIO pins for communicating with other devices. One can limit amount of IO's they use and use an open-source communication method to make sure it can only do one thing.

And about verification of loaded bitstream. Best option is to build and upload the bitstream.

How much one should think ahead to break into this device?

RISCV is open-source. You can build bit-stream of it. Or even add custom instructions to it. I'm not sure how these devices store data, For storing private key.