I hope you realize what you say is utterly sutpid.
... blah blah blah.. tl;dr;
My original point is that you won't see double transistor count after a die shrink. Sure, manufacturers want to maintain an edge over their competition by rearchitecting the core or making other enhancements, but it's just naive to think that a core shrink from 40nm to 28nm will yield double performance.
Thanks for your super smart insight though
