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If you still don't get any feedback from the chip, please double check that the RSTn is kept at 18V for at least 1s before your first command to the chip.
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I think you mean 1.8V !
Sure 1.8V.
But from the datasheet it states that signal is active low. So it must be kept for 1s 0V. Or do you mean that after it goes 0V for 1s it must be kept at 1.8V for another 1s before first command?
Reset is low active, you need to drive it low for at least 1s, then drive it to 1V8 and keep it stable there. Give the chip 1s before you send the first command, see the pseudo code snippet you referred to here:
https://bitcointalk.org/index.php?topic=294235.msg5205169#msg5205169One other question here: are there known PLL settings for faster speeds?
I tried manually running through your set_pll_config code for this but the result didn't come out so well (I might very well have done this incorrectly). I wasn't quite sure what the extents of the various fields are as the data sheet looks to be different to your code (and to the various PLL settings posted).
Assuming you have a 12MHz ref clock, try this:
- set pll_postdiv and pll_prediv to 2
- set fbdiv to (target_sys_freq / 3), i.e. you can set your sys_clock in increments of 3MHz, with fbdiv being 9 bit you can go to 1.5+GHz
reg[0] = 0x84 | (fbdiv >> 8)
reg[1] = fbdiv & 0xff