Not sure who said anything about changing mem package voltage.
I said to set the 'mem P3 voltage' - which of course actually controls the core/soc line if it's higher than the current core states voltage setting (and it likely will be w/ core p0 at 800mv.) Since the mem (and thus soc) speed is what is really controlling the voltage needs, given that the core clock is so low in this scenario, to me it makes sense to make the appropriate setting there, rather than at the core clock parameter.
And you could likely use mem P0 instead, or rewrite your core states to have 850/800 at p7, but i've found it unnecessary - no stability problems in my experience.
I'm confused here. As far as my understanding goes - HBM on Vegas doesn't work the way you describe, which is however correct for Polarises.
Don't really know how to respond to that... Which part are you suggesting is incorrect.
Also, please keep in mind this is all based on my experience w/ 8 nitro 64s and both a ref 64 and flashed 56 over 2+ years. On both win and linux. Nothing i'm stating here is theoretical.
Sorry, my mistake:) I read what you posted once more and you are apparently correct if what you are saying is that vega (just like polaris) has its last stage memory(mem controller?) voltage as the controlling voltage of the last stage of the core.