Specification
Process node: 40nm
Package type: QFN64 8mmx8mm (with another option of QFN64 7mmx7mm possible)
I/O: Standard SPI protocol with clk, in, out and cs.
Rated Hashrate: 12.8GHash/s per chip, with a wide range of overclock/downclock options
Rated Voltage: 0.72V, recommended voltage range is 0.55V-1V
Power Consumption: 0.2J/GHash low voltage, 0.35J/GHash rated voltage
This is what we were provided thus far with package type and power estimate. Still awaiting the datasheet.
Is the generation derived from a general set of specifications, number of designs from a manufacturer or just generally where ASIC makers currently are in the whole ASIC market. I didn't get the impression much was invested in what's been termed gen 2.