I would say their wattage claim is completely outside the realm of possibility. 50MH/W? Thats nearly 3x the best FPGA designs and 25x current efficient GPU.
I doubt even a custom ASIC would be 3x FPGA in terms of power. Maybe 50% to 100% better but not 3x.
Well, now that you mention it... that number is only somewhat higher (2x-ish IIRC) than some estimates we did a while assuming a direct ASIC implementation, which was really a lowball figure and ignored support electronics and practical considerations. (Basically a straight account of gate energy usage with a basic unrolled miner on the 45nm process we had specs handy for). So not completely impossible, but impossible for a FPGA on that process.
If someone was offering 22nm SASIC it might be a bit more plausible.